The present invention relates to semiconductor memory devices and, more particularly, to test circuits for semiconductor memory devices.
Dynamic random access memory (“DRAM”) devices are well known in the art and are employed as the primary memory device in many electronic systems. Typically, a unit memory cell (also referred to herein as a “memory cell” or as a “cell”) of a DRAM device includes one access transistor and one storage capacitor.
It can be difficult to manufacture all of the memory cells in a memory cell array without defects using conventional semiconductor manufacturing processes. If a memory cell is defective, it cannot be used to store data. Accordingly, semiconductor manufacturers typically include redundancy memory cells in a memory cell array in addition to the normal memory cells. Defective memory cells are then identified through testing operations, and each defective memory cell is replaced with one of the redundancy memory cells.
A parallel bit test is typically used to locate defective memory cells. This test may be performed in an electrical die sorting (EDS) process. Efforts have been made to shorten the time required to perform these tests in order to streamline the manufacturing process and reduce production costs. In fact, prior to development of the parallel bit test, a serial bit test was performed. The parallel bit test ultimately replaced the serial bit test since the parallel bit test requires less time to perform.
A parallel bit test circuit may be used to perform the parallel bit test on a DRAM device. In a parallel bit test mode, the same data is written to N different memory cells, where N is a natural number of 2 or more, and then the stored data is simultaneously read from these N memory cells. The N bits of data that are read are then compared with each other using a comparator to determine whether or not the same data was read from all of the N memory cells. The comparator outputs a bit which indicates whether or not the same value was read from the N memory cells. Thus, using a parallel bit test, the number of cycles that are required to test all of the cells in a memory cell array may be reduced to 1/N.
FIG. 1 is a block diagram of a parallel bit test circuit that is coupled to a memory cell array. As shown in FIG. 1, the parallel bit test circuit includes an input mode selector 10 that selects between a normal mode and a test mode for input data DI. The input mode selector 10 transfers the input data to a memory cell array 20. The memory cell array 20 stores input data which can then be output as output data C1-C4. The parallel test circuit further includes a comparator 30 and an output mode selector 40. The comparator 30 compares the outputs C1-C4 of the memory cell arrays 20 and generates a comparison output signal COM_OUT, and the output mode selector 40 couples either output data or test result data to an output terminal based on the selected mode.
The parallel bit test circuit of FIG. 1 includes two operating modes, namely a normal mode in which data is written to and read from the cells of the respective memory cell arrays 20, and a parallel bit test mode in which data is simultaneously written to and read from each of the memory cell arrays 20.
In the normal mode, one word line within one memory cell array 20 and one or more bit lines that correspond to the memory cell(s) to which data is to be read or written are selected through a combination of row and column addresses. Data can then be read or written to the selected memory cells.
In the test mode, the input mode selector 10 selects the test mode and the same data is written to each of the memory cell arrays 20. A read operation is then performed and the data read from the respective memory cell arrays 20 is applied to the comparator 30. When the data read from the respective memory cell arrays 20 are all ‘low’ or all ‘high’, the output COM_OUT of the comparator 30 is at a ‘high’ level. In all other cases the output COM_OUT of the comparator 30 is at a ‘low’ level. The result of the comparison COM_OUT is buffered and transferred to the output terminal through the output mode selector 40.
Thus, if identical data is read from all four memory cell arrays 20 when the device is in the test mode, the test result is normal and an output data DQ is output as a logic ‘high’ level. If instead, any of the data bits read from the four memory cell arrays 20 differ, the output data DQ is output as logic ‘low’, indicating that at least one of the memory cells in one (or more) of the memory cell arrays 20 is defective.
The parallel bit test circuit of FIG. 1 is employed in semiconductor memory devices such as DRAM devices. FIG. 2 is a high-level circuit diagram of a conventional
Synchronous Dynamic Access Memory (SDRAM) Device.
In the exemplary device of FIG. 2, four “banks” are provided that are operated as four memory cell arrays 1200A˜1200D. To simplify the diagram, only two of the memory cell arrays, memory cell arrays 1200A and 1200D, are fully depicted. Each memory cell array 1200A˜1200D includes a plurality of memory cells that are disposed in rows and columns to form a matrix.
Operation of the memory cell arrays 1200A˜1200D (also referred to herein as “memory banks” or simply as “banks”) will now be explained with reference to memory cell array 1200A. A word line (not shown in FIG. 2) of memory cell array 1200A is driven according to an output of row decoder ROWDEC 1201A. Word driver 1202A is driven by the output of row decoder ROWDEC 1201A, and the word driver 1202A drives a selected one of a plurality of word lines of the memory cell array 1200A. A data line (not shown in FIG. 2) in memory cell array 1200A is coupled to a sense amplifier 1203A. The sense amplifier 1203A is coupled to a column decoder COLUMN DEC 1205A through an I/O gate circuit I/O GATE 1204A as a column selection circuit. The sense amplifier 1203A is an amplification circuit that detects and amplifies a small potential difference appearing in respective data lines when data is read from a memory cell.
While memory arrays 1200B and 1200C are not fully shown in FIG. 2, it will be understood that they each have a corresponding row decoder 1201B˜C, sense amplifier 1203B˜C, I/O gate circuit 1204B˜C and column decoder 1205B˜C. Input lines and output lines of all of the I/O gate circuit 1204A to 1204D for the memory banks are coupled with an output terminal of data input circuit DIN BUFFER 1210 and an input terminal of data output circuit DOUT BUFFER 1211, respectively. Though not limited, terminals D0˜D7 become data input/output terminals to receive or output 8 bit data D0-D7.
As is also shown in FIG. 2, an address signal A0˜A14 supplied from the address input terminal is first stored at an address register ADD REG 1213. Based on the address signal, a row address signal that selects a memory cell is supplied to the row decoders 1201A˜D of each memory bank through a row address multiplexer ROW ADD MUX 1206. Bits A13 and A14 of the address signal select the memory bank, and thus are supplied to a bank control circuit BANK CNL 1212 as a selection signal that selects the memory bank. A column address signal is supplied from the address register ADD REG 1213 to a column address counter COL ADD CNT 1207. A refresh counter REF CNT 1208 generates a row address for an automatic refresh and a row address and a column address for a self-refresh.
In a memory having a capacity of, for example, 256 megabits and in 8 bit as a column address signal, it is effective to A10 of address signals. The column address signal is supplied as preset data to the column address counter 1207, and in a burst mode designated by a command etc. to be mentioned below, the column address signal (either as preset data or as a sequentially incremented value for the column address signal) is applied to column decoder 1205A˜1205D of each memory bank.
A control logic block 1209 may include a command decoder COMMAND DEC 12091, a refresh controller REF CONT 12092 and a mode register MODE REG 12093. The mode register 12093 stores operating mode information. Each of the row decoders 1201A to 1201D operates to select a word line when a corresponding memory bank is designated by a bank control circuit 1212. Though not limited, external control signals such as a clock signal CLK, a clock enable signal CKE, a chip selection signal /CS (reference code ‘/’ indicating a row enable signal), a column address strobe signal /CAS, a row address strobe signal /RAS, a write enable signal /WE etc., and address signals passed through DQM and the mode register 12093 may be supplied to the control logic block 1209. The control logic block 1209 produces internal timing signals to control an operating mode of the SDRAM and operation of the circuit blocks based on a change of signal level or timing etc.
FIG. 3 shows the configuration of an exemplary sub array of one of the memory banks shown in FIG. 2. In particular, FIG. 3 is a block diagram of a sub array 1101. Each of the memory banks 1200A˜1200D of FIG. 2 would include a plurality of these sub arrays. The row decoder 1200 and the column decoder 1300 for the bank are also shown in FIG. 3. The sub array 1101 comprises sub array areas 1101A and 1101B and plates 11020, 11021, 11030 and 11031. A main word line MWL may be disposed in a row direction of the sub array 1101. A sub word driver SWD is coupled to a main word line and coupled with sub word lines SWL that are provided within the plates 11020, 11021, 11030, 11031. A particular sub word line SWL may be selected by an RAA, RAB signal from RAD driver 1501A, 1501B. Each sub word driver SWD can drive four or eight sub word lines for one main word line.
Each sub array area 1101A, 1101B may include a sense amplifier activation control unit SAA that drives a plurality of bit line sense amplifiers SA, and the above mentioned RAD driver 1501A, 1501B. The sense amplifier activation control unit SAA may supply a control signal Y8A or Y8B to a sense amplifier driver D. The sense amplifier activation control unit SAA may also supply the control signal Y8A or Y8B to the RAD driver. In this manner, the sense amplifier activation control unit SAA can enable a column of plate PLT. This general structure can be repeated within the bank so that the sense amplifier activation control unit SAA can enable all even columns or all odd columns by using control signal Y8A or Y8B.
As shown in FIG. 3, RAD driver 1501A may supply a 4 bit or an 8 bit sub word line selection signal RAA to a column of the sub word line driver SWD adapted in a column of plate to which the plate 11020, 11030 belongs. The RAD driver 1501B may supply a 4 bit or an 8 bit sub word line selection signal RAA to a column of the sub word line driver SWD adapted in a column of plate to which the plate 11021, 11031 belongs.
In a semiconductor memory device having the structure described above with respect to FIGS. 2 and 3, a parallel bit test has been recently developed in which a plurality of data output pins are merged in parallel for producing a common memory test output signal. For example, when data output pins are merged in a unit of four or eight, a pass/fail decision as a test result is obtained through one representative data output pin among the four or eight data output pins. Thus, with this method, when a data bus coupled with data output pins has 64 lines, 64 bit test result data is output, and when a data bus has 32 lines, 32 bit test result data is output.